5.7 Write Sequences

4-Word Write Sequence

A 4-word write sequence is performed by a CACHE Index Store Data (S) instruction to store a quadword of data and 10 check bits into the secondary cache data array.

Figure 5-7 depicts a secondary cache 4-word write sequence. A quadword is written to the index specified by PA(23:6), and the way specified by VA(0) of the CACHE instruction.

A doubleword specified by VA(3) is obtained from the CP0 TagHi and TagLo registers, and the other half of the doubleword is padded to zeros. Normal ECC and parity generation is bypassed and the check field of the data array is written with the contents of the CP0 ECC(9:0) register.



Figure 5-7 4-Word Write Sequence

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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